Register Description Language (RDL) & Register Compiler
Compile and generate hardware register maps, SystemRDL, Verilog/HDL, C/C++ firmware headers, Rust drivers, UVM RAL models, and Markdown documentation from CSV, TOML, SystemRDL, or JSON IR.
Beta Release Notice: This Register Compiler is currently in Beta. While it supports core SystemRDL, CSV, TOML, and JSON IR workflows, please review all generated RTL and header files before deploying to production tape-outs or mission-critical hardware designs.
Memory-Mapped Registers (MMRs) form the foundational communication bridge between hardware logic and software firmware in modern SoCs, ASICs, and FPGAs. Maintaining consistent register definitions across RTL, firmware, verification environments, and documentation can be error-prone when done manually.
The Register Compiler acts as a unified single-source-of-truth processor for hardware register maps.
Supported Input Formats
- CSV: Intuitive spreadsheet-friendly tabular register definition format with configurable bus interfaces (AXI4-Lite, APB3, AHB-Lite, Wishbone).
- TOML: Clean, human-readable structured configuration syntax for peripheral register maps.
- SystemRDL 2.0: The industry-standard Accellera register description language for complex IP blocks and address spaces.
- JSON IR: A structured Intermediate Representation (AST) for automated pipelines and custom generator integration.
How to Use
- Select an Input Format: Click the CSV, TOML, JSON IR, or SystemRDL tab.
- Provide Register Definitions: Paste your register specification, click 📂 Open File to load a local file, or click ⚡ Sample to load a ready-to-run template.
- Configure Block Metadata (CSV only): Specify the Block Name, Base Address, Bus Interface (AXI4Lite, APB3, AHBLite, Wishbone), and Bus Width (bits).
- Choose Desired Outputs: Check the output formats you want to generate.
- Compile & Download: Click â–¶ Compile & Download to download a single file or a bundled
register_map.ziparchive containing all selected outputs.
100% Client-Side & Private: All parsing, Design Rule Checks (DRC), and code generation execute entirely within your browser using high-performance WebAssembly (WASM). None of your proprietary register descriptions or architectural files are transmitted to any external server.
Design Rule Checks (DRC) & Validation
Before emitting target code, the compiler runs a comprehensive Design Rule Check (DRC) suite to guarantee register consistency and prevent hardware bugs:
- Address Collision Detection: Ensures no two registers occupy overlapping address spans.
- Bus Width Alignment: Verifies that register offsets conform to byte and word alignment rules (e.g., 4-byte boundaries for 32-bit buses).
- Field Range Verification: Confirms that bitfield ranges
[msb:lsb]do not overlap within the same register and stay within the bus bit-width. - Access Policy Validation: Validates hardware read/write access types (
RW,RO,WO,W1C,W1S,RC,W1T). - Reset Value Consistency: Ensures specified reset default values fit within their allocated bitfield widths.
Generated Target Outputs
| Output Target | File Extension | Target Domain | Primary Purpose |
|---|---|---|---|
| Verilog RTL | .v | FPGA / ASIC RTL | Synthesizable hardware register decoder & logic |
| C/C++ Header | .h | Embedded / Firmware | Register address offsets, bitmasks, and field shifts |
| Rust Driver | .rs | Systems Software / PAC | Memory-safe type-checked peripheral register access |
| UVM RAL | .sv | Verification / DV | SystemVerilog UVM register abstraction layer testbench models |
| Markdown Docs | .md | Documentation | Register map tables and field descriptions for datasheets |
| SystemRDL | .rdl | EDA Toolchains | Standard Accellera SystemRDL 2.0 IP description |
| TOML / CSV | .toml, .csv | Interoperability | Interchange formats for human editing and spreadsheets |
| JSON IR | .json | Tooling & CI/CD | Abstract syntax tree for custom in-house automation |
Common Applications
- ASIC & FPGA IP Block Design: Eliminate repetitive manual RTL coding of bus slave interfaces. Generate clean, synthesizable Verilog modules compatible with AXI4-Lite, APB3, AHB-Lite, and Wishbone interconnects.
- Embedded Firmware & Device Drivers: Maintain synchronized register offsets and bitmask definitions across firmware development teams.
- UVM Verification Environments: Instantly generate UVM RAL (Register Abstraction Layer) SystemVerilog code with built-in field coverage.