<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Formal-Verification on Cadiora</title><link>https://cadiora.com/tags/formal-verification/</link><description>Recent content in Formal-Verification on Cadiora</description><generator>Hugo</generator><language>en-us</language><lastBuildDate>Sun, 27 Sep 2026 17:37:52 +0800</lastBuildDate><atom:link href="https://cadiora.com/tags/formal-verification/index.xml" rel="self" type="application/rss+xml"/><item><title>Autopsy of Vivado AXI-Lite Templates (2021.2 vs. 2025.2): Protocol Defects and Design Traps</title><link>https://cadiora.com/articles/fpga/autopsy-of-xilinx-vivado-axi-lite-template/</link><pubDate>Fri, 25 Sep 2026 13:00:00 +0000</pubDate><guid>https://cadiora.com/articles/fpga/autopsy-of-xilinx-vivado-axi-lite-template/</guid><description>A code-level comparison of Vivado 2021.2 and 2025.2 32-bit, four-register AXI-Lite templates, covering write pairing, read and write response backpressure, address decode scaling, and integration limits.</description></item></channel></rss>