Field Programmable Gate Array (FPGA)

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Autopsy of Vivado AXI-Lite Templates (2021.2 vs. 2025.2): Protocol Defects and Design Traps
Autopsy of Vivado AXI-Lite Templates (2021.2 vs. 2025.2): Protocol Defects and Design Traps
FPGA • 12 min read

A code-level comparison of Vivado 2021.2 and 2025.2 32-bit, four-register AXI-Lite templates, covering write pairing, … Continue reading

#axi4-lite #vivado #xilinx #formal-verification #zipcpu #fpga #amba #hardware-bugs
2
Why Switch to SystemVerilog? A Synthesizable RTL Perspective
Why Switch to SystemVerilog? A Synthesizable RTL Perspective
FPGA • 12 min read

A practical case for moving synthesizable RTL from Verilog to SystemVerilog, with side-by-side examples and notes on … Continue reading

#systemverilog #verilog #rtl #fpga #synthesis
3
Installing/Uninstalling Vivado 2017.4 in Ubuntu 16.04
Installing/Uninstalling Vivado 2017.4 in Ubuntu 16.04
FPGA • 4 min read

Step-by-step guide to install Xilinx Vivado 2017.4 with dependencies in Ubuntu Linux. Continue reading

#xilinx #vivado #ubuntu #linux #installation-guide #fpga-tools
4
Generating and Configuring Xilinx FPGA with MCS
Generating and Configuring Xilinx FPGA with MCS
FPGA • 3 min read

Generate memory configuration files for Xilinx FPGA non-volatile programming using MCS format. Continue reading

#xilinx #vivado #fpga-programming #mcs-file #flash-memory #bitstream #hardware-configuration